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lc868900/10/50/60 no.6709-1/20 overview the lc868900 is a column (segment) driver with the display ram for the liquid crystal dot matrix-graphic display. it stores display data sent from the 8-bit microcontroller in the internal display ram and generates dot matrix lcd signals. the lc868900 can control the graphic mode, in which each bit of data from the internal ram either lights or does not light a dot in the lcd. as the lc868900 is fabricated using cmos process technology, combining it with a cmos microcontroller produces an lcd devices of low power demand. feature (1) classification ? interfacing allowed with 80-family lc868900 640 5 8-bit ram lc868910 1280 5 8-bit ram ? interfacing allowed with motorola-family LC868950 640 5 8-bit ram lc868960 1280 5 8-bit ram (2) segment outputs ? 80 segment outputs ? segment display direction programmable (3) automatic lcd display controller ? display duty : 1 / 1 - 1 / 65 duty ? instruction functions - on / off of display - control of the horizontal display bits : (6 - 8 bits) 5 (horizontal display bytes) - vertical display scroll function : set of start address register - selectable display data output : 'logical-or output' or 'exclusive-or output' - read / write display data - read of busy flag sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan lc868900/10/50/60 d2800 rm (im) fs any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. cmos ic ver. 1.03 61295 column driver ic for dot matrix graphic lcd preliminary ordering number : enn*6709
lc868900/10/50/60 no.6709-2/20 (4) power supply ? logic circuit 3 to 5v (v dd ) ? lcd drive circuit v dd to v dd -15v (5) cmos process (6) factory shipment ? chip delivery form ? qfp100 pin assignment package dimensions unit : mm 3151 50 s30 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s17 s15 s16 s14 s13 s11 s12 s10 s9 s8 s7 s5 s6 s4 s3 s2 s1 62 61 60 59 58 57 56 55 54 53 52 51 64 63 65 66 67 68 70 69 72 71 73 74 75 77 76 78 79 22 21 20 23 24 25 26 27 28 29 30 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 s51 s62 s61 s60 s59 s58 s57 s56 s55 s54 s53 s52 s63 s66 s65 s64 s69 s68 s67 s70 s71 s72 s73 s74 s75 s76 s77 s78 s79 s80 100 80 s31 s32 s33 s34 s35 s36 s37 s38 s39 s40 s41 s42 s43 s44 s45 s46 s47 s48 s49 s50 db0 db1 db2 db3 db4 db5 db6 db7 res v dd cs rd wr rs cl2 m v ss v2 82 81 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 v3 v5 ilc00170 21.6 0.8 3.0max 1.6 17.2 0.825 1 30 31 50 51 80 81 1.6 0.575 0.575 0.15 2.7 15.6 0.3 20.0 23.2 14.0 0.65 0.825 100 0.8 0.65 0.1 sanyo : qip-100e
lc868900/10/50/60 no.6709-3/20 pad layout chip size (x 5 y) : 5.71mm 5 4.43mm thickness of chip : 480 m s pad size : 120 m m 5 120 m m 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ilc00171
lc868900/10/50/60 no.6709-4/20 pad name and cordinates table pin no. pad no. name cordinates pin no. pad no. name cordinates x m my m mx m my m m 1 1 s80 -- 2645 -- 1974 51 51 s30 2572 2019 2 2 s79 -- 2483 -- 1974 52 52 s29 2409 2019 3 3 s78 -- 2320 -- 1974 53 53 s28 2247 2019 4 4 s77 -- 2158 -- 1974 54 54 s27 2084 2019 5 5 s76 -- 1995 -- 1974 55 55 s26 1922 2019 6 6 s75 -- 1833 -- 1974 56 56 s25 1759 2019 7 7 s74 -- 1670 -- 1974 57 57 s24 1597 2019 8 8 s73 -- 1508 -- 1974 58 58 s23 1434 2019 9 9 s72 -- 1345 -- 1974 59 59 s22 1272 2019 10 10 s71 -- 1183 -- 1974 60 60 s21 1109 2019 11 11 s70 -- 1020 -- 1974 61 61 s20 947 2019 12 12 s69 -- 858 -- 1974 62 62 s19 784 2019 13 13 s68 -- 695 -- 1974 63 63 s18 622 2019 14 14 s67 -- 533 -- 1974 64 64 s17 459 2019 15 15 s66 -- 370 -- 1974 65 65 s16 297 2019 16 16 s65 -- 208 -- 1974 66 66 s15 134 2019 17 17 s64 -- 45 -- 1974 67 67 s14 -- 28 2019 18 18 s63 117 -- 1974 68 68 s13 -- 191 2019 19 19 s62 280 -- 1974 69 69 s12 -- 353 2019 20 20 s61 442 -- 1974 70 70 s11 -- 516 2019 21 21 s60 605 -- 1974 71 71 s10 -- 678 2019 22 22 s59 767 -- 1974 72 72 s9 -- 841 2019 23 23 s58 930 -- 1974 73 73 s8 -- 1003 2019 24 24 s57 1092 -- 1974 74 74 s7 -- 1166 2019 25 25 s56 1255 -- 1974 75 75 s6 -- 1328 2019 26 26 s55 1417 -- 1974 76 76 s5 -- 1491 2019 27 27 s54 1580 -- 1974 77 77 s4 -- 1653 2019 28 28 s53 1742 -- 1974 78 78 s3 -- 1816 2019 29 29 s52 1905 -- 1974 79 79 s2 -- 1978 2019 30 30 s51 2658 -- 1985 80 80 s1 -- 2141 2019 31 31 s50 2658 -- 1823 81 81 db0 -- 2540 1905 32 32 s49 2658 -- 1660 82 82 db1 -- 2540 1734 33 33 s48 2658 -- 1498 83 83 db2 -- 2540 1563 34 34 s47 2658 -- 1335 84 84 db3 -- 2540 1392 35 35 s46 2658 -- 1173 85 85 db4 -- 2540 1221 36 36 s45 2658 -- 1010 86 86 db5 -- 2540 1051 37 37 s44 2658 -- 848 87 87 db6 -- 2540 880 38 38 s43 2658 -- 685 88 88 db7 -- 2540 709 39 39 s42 2658 -- 523 89 89 res -- 2540 538 40 40 s41 2658 -- 360 90 90 v dd -- 2540 375 41 41 s40 2658 -- 198 91 91 cs -- 2540 213 42 42 s39 2658 -- 35 92 92 rd -- 2540 50 43 43 s38 2658 127 93 93 wr -- 2540 -- 112 44 44 s37 2658 290 94 94 rs -- 2540 -- 275 45 45 s36 2658 452 95 95 cl2 -- 2540 437 46 46 s35 2658 615 96 96 m 2540 -- 600 47 47 s34 2658 777 97 97 v ss -- 2540 -- 762 48 48 s33 2658 940 98 98 v2 -- 2517 -- 943 49 49 s32 2658 1102 99 99 v3 -- 2517 -- 1106 50 50 s31 2658 1265 100 100 v5 -- 2571 -- 1268 notes ; ? when the chip is used, connect the substrate of chip to v dd (or open). ? if the package immerse in the solder tank when mounting the qfp on the substrate, inquire of our company about the conditions of it.
lc868900/10/50/60 no.6709-5/20 block diagram screen 1 start address cursol address high cursol address low horizontal character number register horizontal bit register timing generator duty register mode register data register instruction register output buffer dout upper address ram (640 bytes) or (1280 bytes) lower address din dout screen 2 start address db7 db6 pararell-serial lcd driver db5 db4 db3 db2 db1 db0 v ss v dd cl2 rs m rd wr res v5 v3 v2 s1 s80 ilc00172 pin description pin pin no. input / output function description v ss 97 -- should be connected with the negative supply voltage pin. v dd 90 - should be connected with the positive supply voltage pin. db0 81 input / output built-in data bus and pull-up resistor to to terminal for transmitting / receiving data to / from the mpu db7 88 res 89 input reset, built-in pull-up resistor cs 91 input chip select : selection allowed when cs=0, built-in pull-up resistor rd 92 input read signal : mpu ? lc868900 series, built-in pull-up resistor wr 93 input write signal : mpu ? lc868900 series, built-in pull-up resistor rs 94 input register select : rs=1 ; instruction register, rs=0 ; data register built-in pull-up resistor cl2 95 input signal for lcd display (clock signal), built-in pull-down resistor m 96 input signal for lcd display (synchronization), built-in pull-up resistor v2 98 - voltage supply pins to lcd drivers v3 99 - v5 100 - s1 80 output segment driver pins for lcd display to to s80 1
lc868900/10/50/60 no.6709-6/20 1. absolute maximum ratings at v ss =0v and ta=25 c parameter symbol pins conditions ratings v dd [v] min. typ. max. unit supply voltage v dd max v dd -- 0.3 +7.0 v input voltage vnmax v2, v3, v5 v dd -- 12 v dd +0.3 for lcd input voltage v i (1) cs, rd, wr, rs -- 0.3 v dd +0.3 cl2, m, res vi(2) db0 to db7 -- 0.3 v dd +0.3 (input mode) output voltage vo(1) s1 to s80 v dd -- 12 v dd +0.3 vo(2) db0 to db7 -- 0.3 v dd +0.3 (output mode) power pdmax qfp100e ta= -- 30 to + 70 c 200 mw dissipation (max.) operating topg -- 30 70 c temperature range storage tstg -- 55 150 temperature range *satisfy the next condition : v dd 3 v2 3 v3 3 v5
lc868900/10/50/60 no.6709-7/20 2. recommended operating range at ta= -- 30 c to +70 c, v ss =0v parameter symbol pins conditions ratings v dd [v] min. typ. max. unit operating v dd v dd fcl2 500khz 2.5 6.0 v supply voltage range hold voltage v hd v dd rams and 2.0 6.0 registers hold voltage at standby mode. input high v ih (1) db0 to db7 input mode 4.5 to 6.0 2.2 v dd voltage 2.5 to 4.5 0.75v dd v dd v ih (2) cs, rd, wr, rs 4.5 to 6.0 2.2 v dd 2.5 to 4.5 0.75v dd v dd v ih (3) cl2, m, res 4.5 to 6.0 0.75v dd v dd 2.5 to 4.5 0.75v dd v dd input low v il (1) db0 to db7 input mode 4.5 to 6.0 0 0.8 voltage 2.5 to 4.5 0 0.25v dd v il (2) cs, rd, wr, rs 4.5 to 6.0 0 0.8 2.5 to 4.5 0 0.25v dd v il (3) cl2, m, res 4.5 to 6.0 0 0.25v dd 2.5 to 4.5 0 0.25v dd input clock fcl2 cl2 2.5 to 6.0 0 500 khz frequency [notes] the specifications above are for a die mounted in a qfp100e type package. however, we ship this product as a die only, not a package chip. therefore, the operational characteristics may vary depending on the user's packaging techniques.
lc868900/10/50/60 no.6709-8/20 3. electrical characteristics at ta= -- 30 c to +70 c, v ss =0v parameter symbol pins conditions ratings v dd [v] min. typ. max. unit output high i oh (1) db80 to db7 ?output mode 4.5 to 6.0 2.4 v dd v voltage ?i oh = -- 0.6ma ?output mode 2.5 to 6.0 v dd -- 0.5 v dd ?i oh = -- 0.1ma output low v ol (1) db0 to db7 ?output mode 4.5 to 6.0 0 0.4 voltage ?i oh =+0.6ma ?output mode 2.5 to 6.0 0 0.4 ?i oh =+0.1ma v dd -si drop v d (1) s1 to s80 ? si terminal for - - 90 m a 4.5 to 6.0 mv voltage ? v dd -- v5=11v (i:1 to 80) ? si terminal for - - 15 m a 2.5 to 6.0 120 ? v dd -- v5=11v vx-si drop v d (2) s1 to s80 ? si terminal for -- 90 m a 4.5 to 6.0 mv voltage ? v dd -- v5=11v (x:2, 3) ? si terminal for -- 15 m a 2.5 to 6.0 120 (i:1 to 80) ? v dd -- v5=11v pull-up rpu(1) db0 to db7 ?input mode 4.5 to 6.0 150 500 900 k w resistor ?v in =0v ?input mode 2.5 to 4.5 300 750 1500 ?v in =0v rpu(2) cs, rd, wr, rs, v in =0v 4.5 to 6.0 150 500 900 res v in =0v 2.5 to 4.5 300 750 1500 pull-down rpd(1) cl2 v in =0v 4.5 to 6.0 150 500 900 k w resistor v in =0v 2.5 to 4.5 300 750 1500 hysteresis vhis res 2.5 to 6.0 0.1v dd v voltage current i dd (1) ?fcl2=500khz 4.5 to 6.0 ma dissipation ?figure 1 at operaion ?fcl2=500khz 2.5 to 4.5 ?figure 1 current i dd (2) ?fcl2=0hz 4.5 to 6.0 0.05 30 m a dissipation ? v2=v3=v5=v dd at stand-by ?figure 2 mode ?fcl2=0hz 2.5 to 4.5 0.02 20 ? v2=v3=v5=v dd ?figure 2 db0 db1 db2 db3 db4 db5 db6 db7 lc868900 res cs rd wr rs m v dd s1 s2 s80 cl2 v ss v2 v3 v5 fcl2=0hz open open a v dd open v dd db0 db1 db2 db3 db4 db5 db6 db7 lc868900 res cs rd wr rs m v dd s1 s2 s80 cl2 v ss v2 v3 v5 fcl2=500khz open open a v dd open v dd ilc00173 ilc00174 figure1. current dissipation measuring circuit at operation figure2. current dissipation measuring circuit at stand-by mode
lc868900/10/50/60 no.6709-9/20 4. ac characteristics at ta= -- 30 c to +70 c, v ss =0v (1) mpu interface 1. reading cycle 2. writing cycle no. item symbol conditions value v dd [v] min. max. unit 1 rd, wr cycle time tcyc1 rd 4.5 to 6.0 (500) ns 2.5 to 4.5 tcyc2 wr 4.5 to 6.0 (500) ns 2.5 to 4.5 2 rd pulse width tpw1 rd 4.5 to 6.0 (220) ns wr pulse width wr 2.5 to 4.5 3 rise / fall time tr1, tf1 rd 4.5 to 6.0 (20) ns 2.5 to 4.5 4 address set-up tas1 cs, rs, rd 4.5 to 6.0 (40) ns time 2.5 to 4.5 tas2 cs, rs, wr 4.5 to 6.0 (40) ns 2.5 to 4.5 5 address hold time tah1 cs, rs, rd 4.5 to 6.0 (10) ns 2.5 to 4.5 tah2 cs, rs, wr 4.5 to 6.0 (10) ns 2.5 to 4.5 6 data delay time tddr1 rd, db0 to db7, cl=50pf 4.5 to 6.0 (120) ns 2.5 to 4.5 7 data hold time tdhr1 rd, db0 to db7, cl=50pf 4.5 to 6.0 (20) ns 2.5 to 4.5 8 data set-up time tdsw1 wr, db0 to db7, cl=50pf 4.5 to 6.0 (60) ns 2.5 to 4.5 9 data hold time tdhw1 wr, db0 to db7, cl=50pf 4.5 to 6.0 (10) ns 2.5 to 4.5 cl=load capacitance rd db0-7 cs, rs ilc00175 1 2 6 7 5 4 3 3 wr db0-7 cs, rs ilc00176 1 2 8 9 5 4 3 3
lc868900/10/50/60 no.6709-10/20 (2) display control timing / ta= -- 30 c to +70 c, v ss =0v no. item symbol conditions value v dd [v] min. max. unit 1 low level twlcl2 lc2 4.5 to 6.0 (800) ns pulse width 2.5 to 4.5 2 high level twlcl2 lc2 4.5 to 6.0 (800) ns pulse width 2.5 to 4.5 3 rise time tr cl2 4.5 to 6.0 (20) ns 2.5 to 4.5 4 fall time tf cl2 4.5 to 6.0 (20) ns 2.5 to 4.5 5 m delay time tdm m 4.5 to 6.0 (60) ns 2.5 to 4.5 cl2 m ilc00177 1 5 4 3 0.7v dd 0.3v dd 0.7v dd 0.3v dd 2
lc868900/10/50/60 no.6709-11/20 ? example of the reference circuit 1. 64 5 80 dots 2. 64 5 160 dots 3. 65 5 160 dots cs rs cl2 m db rd wr v1 ~ v5 p41 p43 db p46 p47 xvn 1 ~ 64 com 1 ~ 80 lcd panel 64x80 dots seg lc868900 lc868016 ilc00178 db cs rs rd wr cl2 m v1 ~ v5 db cs rs rd wr cl2 m v1 ~ v5 db cs rs rd wr cl2 m v1 ~ v5 1 ~ 64 com 1 ~ 80 seg lcd panel 64x160 dots seg 81 ~ 160 lc868900 lc868900 lc868901 db p46 p47 lc868016 db cs rs rd wr cl2 m v1 ~ v5 db cs rs rd wr cl2 m v1 ~ v5 db cs rs rd wr cl2 m v1 ~ v5 1 ~ 65 com 1 ~ 80 seg lcd panel 65x160 dots seg 81 ~ 160 lc868910 lc868910 lc868901 db p46 p47 lc868016 ilc00179 ilc00180
lc868900/10/50/60 no.6709-12/20 functions 1. display control instructions ? display is controlled by writing data into the instruction register and 10 data registers. ? the instruction register and the data register are distinguished by the rs signal. ? first, write 4-bit data into the instruction register when rs=1, then specify the code of the data register. next, with rs=0, write 8-bit data in the data register, which executes the specified instruction. ? a new instruction cannnot be accepted while an old instruction is being excuted. as the busy flag is set under this condition, write an instruction only after reading the busy flag and making sure that it is '0'. ? the busy flag does not change when data is written into the instruction register (rs=1). the flag is set when the data is written into the data register at rs=0. therefore, the busy flag need not be checked immediately after writing data into the instruction register. >< instruction register and 10 data registers >< 1. set display mode write code '00h' (in hexadecimal notation) into the instruction register and specify the mode control register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0100000000 mode 0 0 0 0 0 -- mode data (mode) ? mode0 bit0 of mode mode0=1 : screen1 display on mode0=0 : screen1 display off ? mode1 bit1 of mode mode1=1 : screen2 display on mode1=0 : screen2 display off ? mode2 bit2 of mode mode2=1 : exclusive-or display between screen1 and screen2 mode2=0 : or display between screen1 and screen2 ? mode3 bit3 of mode mode3=1 : output data right-shift (s1 to s80) mode3=0 : output data left-shift (s80 to s1) [note] ? mode7 to mode5 must take '0'. a malfunction occurs when one of these bits takes '1'. 2. set display pitch write code '01h' (in hexadecimal notation) into the instruction register and specify the display pitch register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0100000001 pitch 0 0 -- -- -- -- -- dp-- 1
lc868900/10/50/60 no.6709-13/20 ? dp indicates how many bits (or dots) from ram appear in a 1-byte display. ? dp must take one of the following three value. dp db2 db1 db0 display pitch 6101 6 7110 7 8111 8 3. set display number write code '02h' (in hexadecimal notation) into the instruction register and specify the display number register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 100000010 number 0 0 -- -- -- -- dn-- 1 ? dn indicates the number of bytes in the horizontal direction. ? the total number of dots positioned horizontally on the screen, n is given by the following formura. n=dp * dn (n 80) ? numbers in the range 2 to 10 (in decimal) can be set as dn. 4. set number of time division write code '03h' (in hexadecimal notation) into the instruction register and specify the time division register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 100000011 division 0 0 0 nx-- 1 ? nx represents the number of time divisions. ? consequently, 1 / nx is the display duty. ? numbers in the range 2 to 65 (in decimal) can be set as nx. 5. set screen1 display start address write code '08h' (in hexadecimal notation) into the instruction register and specify the screen1 start address register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 100001000 screen1 0 0 0 screen1 start address ? this instruction writes the display-start upper address value in the screen1 start address register. ? the display start address is the ram address at whitch data to be displayed at the leftmost position (mode3=0) or the rightmost position (mode3=1) of the top line of the screen is stored.
lc868900/10/50/60 no.6709-14/20 mode3=1 : start the rightmost position mode3=0 : start the leftmost position ? the start upper address counter is a 7-bit down-counter with preset function. the start upper address is decremented by one when a start lower address has an underflow. when the start upper address is decremented during 0 state, it is set the start addressvalue automatically. internal ram=1280 bytes : start upper address counter=7fh internal ram= 640 bytes : start upper address counter=3fh 6. set screen2 display start address write code '09h' (in hexadecimal notation) into the instruction register and specify the screen2 start address register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0100001001 screen2 0 0 0 screen2 start address ? this instruction writes the display-start upper address value in the screen2 start address register. ? the display start address is the ram address at whitch data to be displayed at the leftmost position (mode3=0) or the rightmost position (mode3=1) of the top line of the screen is stored. mode3=1 : start the rightmost position mode3=0 : start the leftmost position ? the start upper address counter is a 7-bit down-counter with preset function. the start upper address is decremented by one when a start lower address has an underflow.when the start upper address is decremented during 0 state, it is set the start address value automatically. internal ram=1280 bytes : start upper address counter=7fh internal ram= 640 bytes : start upper address counter=3fh 7. set cursor (lower) address (ram read/write lower address) write code '0ah' (in hexadecimal notation) into the instruction register and the lower cursor address register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0100001010 lower 000000 lower cursor address ? this instruction writes the cursor address value in the cursor address counter. the curosr address indicates the address for exchanging display data with display ram. in other words, data at the address specified by the cursor address is read form or written into display ram. the cursor address in divided into a lower address (4 bits) . the cursor lower address counter is a 4-bit down-counter with preset function. the cursor lower address is decreased by one every ram read/write timing. when the cursor lower address is decreased during 0 state, it is set dn-1 automatically.
lc868900/10/50/60 no.6709-15/20 8. set cursor (upper) address (ram read / write upper address) write code '0bh' (in hexadecimal notation) into the instruction register and the upper cursor address register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 100001011 upper 0 0 0 upper cursor address ? this instruction writes the cursor address value in the cursor address counter. the curosr address indicates the address for exchanging display data with display ram. in other words, data at the address specified by the cursor address is read form or written into display ram. the cursor address in divided into an upper addres (7 bits). the cursor upper address counter is a 7-bit down-counter with preset funciton. the cursor upper address is decreased by one when cursor lower address has an underflow. when the cursor upper address is decreased during 0 state, it is set cursor upper address number automatically. 9. writing display data write code '0eh' (in hexadecimal notation) into the instruction register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 100001110 ram 0 0 msb lsb ? after writing code '0eh' , write 8-bit data with rs=0, and the data is written into ram as display data at the address specified by the cursor adress counter. after writing, the count of the cursor address counter decrements by one. 10. reading display data write code '0fh' (in hexadecimal notation) into the instruction register. register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0 100001111 ram 1 0 msb lsb the read status is established with rs=0, and data in ram can be read. the procedure for reading data is as follows: 1. the instruction outputs the contents of the data output register to db0 to db7. 2. transfer the ram data indicated by the cursor address to the data output registser. 3. it then decrements the cursor address by one. refer to next figure. conditions ?instruction register (ir) = 0fh ?rs = 0 ?rd = 0 ram data cursor address counter 11 bits 8 bits db0 db1 db7 --1 output control (oe) d0 to d7 a0 to a10 ?@ data output register data output resister ilc00181
lc868900/10/50/60 no.6709-16/20 ? the correct data cannot be read in the first read operation. the specified value is output in the second read operation. accordingly, a dummy read operation must be performed once when reading data after setting the cursor address. 11. read busy flag register r / w rs db7 db6 db5 db4 db3 db2 db1 db0 instruction 0100001111 busy 1 1 1 / 0 no meaning ? the busy flag is output to db7 when read mode is extablished with rs=1. the busy flag is set to 1 while any of the instructions (1) through (10) is being executed. it is set to 0 at the completion of the execution, allowing the next instruction to be accepted. no other instruction can be accepted when the busy flag is 1. accordingly, before writing an instruction and data, it is necessary to ensure that the busy flag is 0. however, the next instruction can be executed without checking the busy flag when the maximum read cycle time or the write cycle time has been exceeded after execution of the previous data read instruction or the data write instruction. the busy flag does not change when data is written into the instruction register (rs=1). this flag is set when data is written into the data register (rs=0). therefore, the busy flag need not be checked immediately after writing data into the instruction register. specification of the instruction register is unnecessary to read the busy flag. 00h 10h 20h 30h 7f0h 01h 11h 21h 31h 7f1h 02h 12h 22h 32h 7f2h 03h 13h 23h 33h 7f3h 04h 14h 24h 34h 7f4h ram address ex.) writing (reading) data to display ram ?lower cursor address (cal) = 03h ?upper cursor address (cah) = 02h ?display number (dn) = 05h ?internal ram size = 1280 bytes ?if writing operation is executed when the cal counter is '0', the cah counter is decremented by 1 after writing operation. the cal counter is set to (dp -1). ?specification by the cursor address first of all, data is written this ram address. ?decrement by 1 after writing operation. ?if writing operation is executed when the cursor address is '00h', the address specified by the internal ram size is set to the cah counter after writing operation. internal ram size 1280 bytes --> 7fh internal ram size 640 bytes --> 3fh the cal counter is set to (dp -1). ilc00239
lc868900/10/50/60 no.6709-17/20 display examples 1. mode control register=01h (screen1 : on, screen2 : off, s80 ? s1) dp=8, dn=10, nx=64, screen1 start address register=3fh 2. mode control register=09h (screen1 : on, screen2 : off, s1 ? s80) dp=8, dn=10, nx=64, screen1 start address register=3fh 3. mode control register=09h (screen1 : on, screen2 : off, s1 ? s80) dp=8, dn=10, nx=64, screen1 start address register=3eh internal display ram : 1280 bytes lsb (3f9h) msb lsb (3e9h) msb lsb (3d9h) msb lsb (049h) msb lsb (039h) msb lsb (029h) msb lsb (019h) msb lsb (009h) msb lsb (3f8h) msb lsb (3e8h) msb lsb (3d8h) msb lsb (048h) msb lsb (038h) msb lsb (028h) msb lsb (018h) msb lsb (008h) msb lsb (3f7h) msb lsb (3e7h) msb lsb (3d7h) msb lsb (047h) msb lsb (037h) msb lsb (027h) msb lsb (017h) msb lsb (007h) msb lsb (3f6h) msb lsb (3e6h) msb lsb (3d6h) msb lsb (046h) msb lsb (036h) msb lsb (026h) msb lsb (016h) msb lsb (006h) msb lsb (3f5h) msb lsb (3e5h) msb lsb (3d5h) msb lsb (045h) msb lsb (035h) msb lsb (025h) msb lsb (015h) msb lsb (005h) msb lsb (3f4h) msb lsb (3e4h) msb lsb (3d4h) msb lsb (044h) msb lsb (034h) msb lsb (024h) msb lsb (014h) msb lsb (004h) msb lsb (3f3h) msb lsb (3e3h) msb lsb (3d3h) msb lsb (043h) msb lsb (033h) msb lsb (023h) msb lsb (013h) msb lsb (003h) msb lsb (3f2h) msb lsb (3e2h) msb lsb (3d2h) msb lsb (042h) msb lsb (032h) msb lsb (022h) msb lsb (012h) msb lsb (002h) msb lsb (3f1h) msb lsb (3e1h) msb lsb (3d1h) msb lsb (041h) msb lsb (031h) msb lsb (021h) msb lsb (011h) msb lsb (001h) msb lsb (3f0h) msb lsb (3e0h) msb lsb (3d0h) msb lsb (040h) msb lsb (030h) msb lsb (020h) msb lsb (010h) msb lsb (000h) msb s65 ------ s72 s57 ------ s64 s49 ------ s56 s41 ------ s48 s33 ------ s40 s25 ------ s32 s17 ------ s24 s9 -------- s16 s1 --------- s8 s73 ------ s80 c1 c2 c3 c60 c61 c62 c63 c64 ilc00182 msb (3f0h) lsb msb (3e0h) lsb msb (3d0h) lsb msb (040h) lsb msb (030h) lsb msb (020h) lsb msb (010h) lsb msb (000h) lsb msb (3f1h) lsb msb (3e1h) lsb msb (3d1h) lsb msb (041h) lsb msb (031h) lsb msb (021h) lsb msb (011h) lsb msb (001h) lsb msb (3f2h) lsb msb (3e2h) lsb msb (3d2h) lsb msb (042h) lsb msb (032h) lsb msb (022h) lsb msb (012h) lsb msb (002h) lsb msb (3f3h) lsb msb (3e3h) lsb msb (3d3h) lsb msb (043h) lsb msb (033h) lsb msb (023h) lsb msb (013h) lsb msb (003h) lsb msb (3f4h) lsb msb (3e4h) lsb msb (3d4h) lsb msb (044h) lsb msb (034h) lsb msb (024h) lsb msb (014h) lsb msb (004h) lsb msb (3f5h) lsb msb (3e5h) lsb msb (3d5h) lsb msb (045h) lsb msb (035h) lsb msb (025h) lsb msb (015h) lsb msb (005h) lsb msb (3f6h) lsb msb (3e6h) lsb msb (3d6h) lsb msb (046h) lsb msb (036h) lsb msb (026h) lsb msb (016h) lsb msb (006h) lsb msb (3f7h) lsb msb (3e7h) lsb msb (3d7h) lsb msb (047h) lsb msb (037h) lsb msb (027h) lsb msb (017h) lsb msb (007h) lsb msb (3f8h) lsb msb (3e8h) lsb msb (3d8h) lsb msb (048h) lsb msb (038h) lsb msb (028h) lsb msb (018h) lsb msb (008h) lsb msb (3f9h) lsb msb (3e9h) lsb msb (3d9h) lsb msb (049h) lsb msb (039h) lsb msb (029h) lsb msb (019h) lsb msb (009h) lsb s65 ------ s72 s57 ------ s64 s49 ------ s56 s41 ------ s48 s33 ------ s40 s25 ------ s32 s17 ------ s24 s9 -------- s16 s1 --------- s8 s73 ------ s80 c1 c2 c3 c60 c61 c62 c63 c64 ilc00183 msb (3e0h) lsb msb (3d0h) lsb msb (3c0h) lsb msb (030h) lsb msb (020h) lsb msb (010h) lsb msb (000h) lsb msb (7f0h) lsb msb (3e1h) lsb msb (3d1h) lsb msb (3c1h) lsb msb (031h) lsb msb (021h) lsb msb (011h) lsb msb (001h) lsb msb (7f1h) lsb msb (3e2h) lsb msb (3d2h) lsb msb (3c2h) lsb msb (032h) lsb msb (022h) lsb msb (012h) lsb msb (002h) lsb msb (7f2h) lsb msb (3e3h) lsb msb (3d3h) lsb msb (3c3h) lsb msb (033h) lsb msb (023h) lsb msb (013h) lsb msb (003h) lsb msb (7f3h) lsb msb (3e4h) lsb msb (3d4h) lsb msb (3c4h) lsb msb (034h) lsb msb (024h) lsb msb (014h) lsb msb (004h) lsb msb (7f4h) lsb msb (3e5h) lsb msb (3d5h) lsb msb (3c5h) lsb msb (035h) lsb msb (025h) lsb msb (015h) lsb msb (005h) lsb msb (7f5h) lsb msb (3e6h) lsb msb (3d6h) lsb msb (3c6h) lsb msb (036h) lsb msb (026h) lsb msb (016h) lsb msb (006h) lsb msb (7f6h) lsb msb (3e7h) lsb msb (3d7h) lsb msb (3c7h) lsb msb (037h) lsb msb (027h) lsb msb (017h) lsb msb (007h) lsb msb (7f7h) lsb msb (3e8h) lsb msb (3d8h) lsb msb (3c8h) lsb msb (038h) lsb msb (028h) lsb msb (018h) lsb msb (008h) lsb msb (7f8h) lsb msb (3e9h) lsb msb (3d9h) lsb msb (3c9h) lsb msb (039h) lsb msb (029h) lsb msb (019h) lsb msb (009h) lsb msb (7f9h) lsb s65 ------ s72 s57 ------ s64 s49 ------ s56 s41 ------ s48 s33 ------ s40 s25 ------ s32 s17 ------ s24 s9 -------- s16 s1 --------- s8 s73 ------ s80 c1 c2 c3 c60 c61 c62 c63 c64 ilc00184
lc868900/10/50/60 no.6709-18/20 4. mode control register=09h (screen1 : on, screen2 : off, s1 ? s80) dp=8, dn=10, nx=64, screen1 start address register=3eh internal display ram : 640 bytes 5. mode control register=03h (screen1 : on, screen2 : on, logical or output of screen1 and screen2, s80 ? s1) dp=8, dn=10, nx=64, screen1 start address register=3fh screen2 start address register=7fh, internal display ram : 1280 bytes 6. mode control register=03h (screen1 : on, screen2 : on, logical or output of screen1 and screen2, s80 ? s1) dp=8, dn=10, nx=32, screen1 start address register=3fh screen2 start address register=1fh, internal display ram : 640 bytes msb (3e0h) lsb msb (3d0h) lsb msb (3c0h) lsb msb (030h) lsb msb (020h) lsb msb (010h) lsb msb (000h) lsb msb (3f0h) lsb msb (3e1h) lsb msb (3d1h) lsb msb (3c1h) lsb msb (031h) lsb msb (021h) lsb msb (011h) lsb msb (001h) lsb msb (3f1h) lsb msb (3e2h) lsb msb (3d2h) lsb msb (3c2h) lsb msb (032h) lsb msb (022h) lsb msb (012h) lsb msb (002h) lsb msb (3f2h) lsb msb (3e3h) lsb msb (3d3h) lsb msb (3c3h) lsb msb (033h) lsb msb (023h) lsb msb (013h) lsb msb (003h) lsb msb (3f3h) lsb msb (3e4h) lsb msb (3d4h) lsb msb (3c4h) lsb msb (034h) lsb msb (024h) lsb msb (014h) lsb msb (004h) lsb msb (3f4h) lsb msb (3e5h) lsb msb (3d5h) lsb msb (3c5h) lsb msb (035h) lsb msb (025h) lsb msb (015h) lsb msb (005h) lsb msb (3f5h) lsb msb (3e6h) lsb msb (3d6h) lsb msb (3c6h) lsb msb (036h) lsb msb (026h) lsb msb (016h) lsb msb (006h) lsb msb (3f6h) lsb msb (3e7h) lsb msb (3d7h) lsb msb (3c7h) lsb msb (037h) lsb msb (027h) lsb msb (017h) lsb msb (007h) lsb msb (3f7h) lsb msb (3e8h) lsb msb (3d8h) lsb msb (3c8h) lsb msb (038h) lsb msb (028h) lsb msb (018h) lsb msb (008h) lsb msb (3f8h) lsb msb (3e9h) lsb msb (3d9h) lsb msb (3c9h) lsb msb (039h) lsb msb (029h) lsb msb (019h) lsb msb (009h) lsb msb (3f9h) lsb s65 ------ s72 s57 ------ s64 s49 ------ s56 s41 ------ s48 s33 ------ s40 s25 ------ s32 s17 ------ s24 s9 -------- s16 s1 --------- s8 s73 ------ s80 c1 c2 c3 c60 c61 c62 c63 c64 ilc00185 ilc00186 lsb (3f9h or 7f9h) msb lsb (3e9h or 7e9h) msb lsb (3d9h or 7d9h) msb lsb (049h or 449h) msb lsb (039h or 439h) msb lsb (029h or 429h) msb lsb (019h or 419h) msb lsb (009h or 409h) msb lsb (3f8h or 7f8h) msb lsb (3e8h or 7e8h) msb lsb (3d8h or 7d8h) msb lsb (048h or 448h) msb lsb (038h or 438h) msb lsb (028h or 428h) msb lsb (018h or 418h) msb lsb (008h or 408h) msb lsb (3f7h or 7f7h) msb lsb (3e7h or 7e7h) msb lsb (3d7h or 7d7h) msb lsb (047h or 447h) msb lsb (037h or 437h) msb lsb (027h or 427h) msb lsb (017h or 417h) msb lsb (007h or 407h) msb lsb (3f6h or 7f6h) msb lsb (3e6h or 7e6h) msb lsb (3d6h or 7d6h) msb lsb (046h or 446h) msb lsb (036h or 436h) msb lsb (026h or 426h) msb lsb (016h or 416h) msb lsb (006h or 406h) msb lsb (3f1h or 7f1h) msb lsb (3e1h or 7e1h) msb lsb (3d1h or 7d1h) msb lsb (041h or 441h) msb lsb (031h or 431h) msb lsb (021h or 421h) msb lsb (011h or 411h) msb lsb (001h or 401h) msb lsb (3f0h or 7f0h) msb lsb (3e0h or 7e0h) msb lsb (3d0h or 7d0h) msb lsb (040h or 440h) msb lsb (030h or 430h) msb lsb (020h or 420h) msb lsb (010h or 410h) msb lsb (000h or 400h) msb s65 ------------ s72 s25 ----------- s32 s17 ----------- s24 s9 ------------ s16 s1 ------------- s8 s73 ------------ s80 c1 c2 c3 c60 c61 c62 c63 c64 lsb (3f9h or 1f9h) msb lsb (3e9h or 1e9h) msb lsb (3d9h or 1d9h) msb lsb (249h or 049h) msb lsb (239h or 039h) msb lsb (229h or 029h) msb lsb (219h or 019h) msb lsb (209h or 009h) msb lsb (3f8h or 1f8h) msb lsb (3e8h or 1e8h) msb lsb (3d8h or 1d8h) msb lsb (248h or 048h) msb lsb (238h or 038h) msb lsb (228h or 028h) msb lsb (218h or 018h) msb lsb (208h or 008h) msb lsb (3f7h or 1f7h) msb lsb (3e7h or 1e7h) msb lsb (3d7h or 1d7h) msb lsb (247h or 047h) msb lsb (237h or 037h) msb lsb (227h or 027h) msb lsb (217h or 017h) msb lsb (207h or 007h) msb lsb (3f6h or 1f6h) msb lsb (3e6h or 1e6h) msb lsb (3d6h or 1d6h) msb lsb (246h or 046h) msb lsb (236h or 036h) msb lsb (226h or 026h) msb lsb (216h or 016h) msb lsb (206h or 006h) msb lsb (3f1h or 1f1h) msb lsb (3e1h or 1e1h) msb lsb (3d1h or 1d1h) msb lsb (241h or 041h) msb lsb (231h or 031h) msb lsb (221h or 021h) msb lsb (211h or 011h) msb lsb (201h or 001h) msb lsb (3f0h or 1f0h) msb lsb (3e0h or 1e0h) msb lsb (3d0h or 1d0h) msb lsb (240h or 040h) msb lsb (230h or 030h) msb lsb (220h or 020h) msb lsb (210h or 010h) msb lsb (200h or 000h) msb s65 ------------ s72 s25 ----------- s32 s17 ----------- s24 s9 ------------ s16 s1 ------------- s8 s73 ------------ s80 c1 c2 c3 c28 c29 c30 c31 c32 ilc00187
lc868900/10/50/60 no.6709-19/20 7. mode control register=07h (screen1 : on, screen2 : on, exclusive-or output of screen1 and screen2, s80 ? s1) dp=8, dn=10, nx=64, screen1 start address register=3fh screen2 start address register=7fh, internal display ram : 1280 bytes 8. mode control register=07h (screen1 : on, screen2 : on, exclusive-or output of screen1 and screen2, s80 ? s1) dp=8, dn=10, nx=16, screen1 start address register=3fh screen2 start address register=0fh 9. mode control register=07h (screen1 : on, screen2 : on, or output of screen1 and screen2, s80 ? s1) dp=8, dn=10, nx=16, screen1 start address register=3eh screen2 start address register=0fh lsb (3f9h eor 7f9h) msb lsb (3e9h eor 7e9h) msb lsb (3d9h eor 7d9h) msb lsb (049h eor 449h) msb lsb (039h eor 439h) msb lsb (029h eor 429h) msb lsb (019h eor 419h) msb lsb (009h eor 409h) msb lsb (3f8h eor 7f8h) msb lsb (3e8h eor 7e8h) msb lsb (3d8h eor 7d8h) msb lsb (048h eor 448h) msb lsb (038h eor 438h) msb lsb (028h eor 428h) msb lsb (018h eor 418h) msb lsb (008h eor 408h) msb lsb (3f7h eor 7f7h) msb lsb (3e7h eor 7e7h) msb lsb (3d7h eor 7d7h) msb lsb (047h eor 447h) msb lsb (037h eor 437h) msb lsb (027h eor 427h) msb lsb (017h eor 417h) msb lsb (007h eor 407h) msb lsb (3f6h eor 7f6h) msb lsb (3e6h eor 7e6h) msb lsb (3d6h eor 7d6h) msb lsb (046h eor 446h) msb lsb (036h eor 436h) msb lsb (026h eor 426h) msb lsb (016h eor 416h) msb lsb (006h eor 406h) msb lsb (3f1h eor 7f1h) msb lsb (3e1h eor 7e1h) msb lsb (3d1h eor 7d1h) msb lsb (041h eor 441h) msb lsb (031h eor 431h) msb lsb (021h eor 421h) msb lsb (011h eor 411h) msb lsb (001h eor 401h) msb lsb (3f0h eor 7f0h) msb lsb (3e0h eor 7e0h) msb lsb (3d0h eor 7d0h) msb lsb (040h eor 440h) msb lsb (030h eor 430h) msb lsb (020h eor 420h) msb lsb (010h eor 410h) msb lsb (000h eor 400h) msb s65 ------------ s72 s25 ----------- s32 s17 ----------- s24 s9 ------------ s16 s1 ------------- s8 s73 ------------ s80 c1 c2 c3 c60 c61 c62 c63 c64 ilc00188 lsb (3f9h eor 0f9h) msb lsb (3e9h eor 0e9h) msb lsb (3d9h eor 0d9h) msb lsb (349h eor 049h) msb lsb (339h eor 039h) msb lsb (329h eor 029h) msb lsb (319h eor 019h) msb lsb (309h eor 009h) msb lsb (3f8h eor 0f8h) msb lsb (3e8h eor 0e8h) msb lsb (3d8h eor 0d8h) msb lsb (348h eor 048h) msb lsb (338h eor 038h) msb lsb (328h eor 028h) msb lsb (318h eor 018h) msb lsb (308h eor 008h) msb lsb (3f7h eor 0f7h) msb lsb (3e7h eor 0e7h) msb lsb (3d7h eor 0d7h) msb lsb (347h eor 047h) msb lsb (337h eor 037h) msb lsb (327h eor 027h) msb lsb (317h eor 017h) msb lsb (307h eor 007h) msb lsb (3f6h eor 0f6h) msb lsb (3e6h eor 0e6h) msb lsb (3d6h eor 0d6h) msb lsb (346h eor 046h) msb lsb (336h eor 036h) msb lsb (326h eor 026h) msb lsb (316h eor 016h) msb lsb (306h eor 006h) msb lsb (3f1h eor 0f1h) msb lsb (3e1h eor 0e1h) msb lsb (3d1h eor 0d1h) msb lsb (341h eor 041h) msb lsb (331h eor 031h) msb lsb (321h eor 021h) msb lsb (311h eor 011h) msb lsb (301h eor 001h) msb lsb (3f0h eor 0f0h) msb lsb (3e0h eor 0e0h) msb lsb (3d0h eor 0d0h) msb lsb (340h eor 040h) msb lsb (330h eor 030h) msb lsb (320h eor 020h) msb lsb (310h eor 010h) msb lsb (300h eor 000h) msb s65 ------------ s72 s25 ----------- s32 s17 ----------- s24 s9 ------------ s16 s1 ------------- s8 s73 ------------ s80 c1 c2 c3 c12 c13 c14 c15 c16 ilc00189 lsb (3e9h eor 0f9h) msb lsb (3d9h eor 0e9h) msb lsb (3c9h eor 0d9h) msb lsb (339h eor 049h) msb lsb (329h eor 039h) msb lsb (319h eor 029h) msb lsb (309h eor 019h) msb lsb (2f9h eor 009h) msb lsb (3e8h eor 0f8h) msb lsb (3d8h eor 0e8h) msb lsb (3c8h eor 0d8h) msb lsb (338h eor 048h) msb lsb (328h eor 038h) msb lsb (318h eor 028h) msb lsb (308h eor 018h) msb lsb (2f8h eor 008h) msb lsb (3e7h eor 0f7h) msb lsb (3d7h eor 0e7h) msb lsb (3c7h eor 0d7h) msb lsb (337h eor 047h) msb lsb (327h eor 037h) msb lsb (317h eor 027h) msb lsb (307h eor 017h) msb lsb (2f7h eor 007h) msb lsb (3e6h eor 0f6h) msb lsb (3d6h eor 0e6h) msb lsb (3c6h eor 0d6h) msb lsb (336h eor 046h) msb lsb (326h eor 036h) msb lsb (316h eor 026h) msb lsb (306h eor 016h) msb lsb (2f6h eor 006h) msb lsb (3e1h eor 0f1h) msb lsb (3d1h eor 0e1h) msb lsb (3c1h eor 0d1h) msb lsb (331h eor 041h) msb lsb (321h eor 031h) msb lsb (311h eor 021h) msb lsb (301h eor 011h) msb lsb (2f1h eor 001h) msb lsb (3e0h eor 0f0h) msb lsb (3d0h eor 0e0h) msb lsb (3c0h eor 0d0h) msb lsb (330h eor 040h) msb lsb (320h eor 030h) msb lsb (310h eor 020h) msb lsb (300h eor 010h) msb lsb (2f0h eor 000h) msb s65 ------------ s72 s25 ----------- s32 s17 ----------- s24 s9 ------------ s16 s1 ------------- s8 s73 ------------ s80 c1 c2 c3 c12 c13 c14 c15 c16 ilc00190
lc868900/10/50/60 no.6709-20/20 specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co. , ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of december, 2000. specifications and information herein are subject to change without notice. ps 10. mode control register=02h (screen1 : off, screen2 : on, s80 ? s1) dp=8, dn=10, nx=16, screen2 start address register=0fh 11. mode control register=09h (screen1 : on, screen2 : off, s1 ? s80) dp=6, dn=8, nx=16, screen1 start address register=1fh lsb (0f9h) msb lsb (0e9h) msb lsb (0d9h) msb lsb (049h) msb lsb (039h) msb lsb (029h) msb lsb (019h) msb lsb (009h) msb lsb (0f8h) msb lsb (0e8h) msb lsb (0d8h) msb lsb (048h) msb lsb (038h) msb lsb (028h) msb lsb (018h) msb lsb (008h) msb lsb (0f7h) msb lsb (0e7h) msb lsb (0d7h) msb lsb (047h) msb lsb (037h) msb lsb (027h) msb lsb (017h) msb lsb (007h) msb lsb (0f6h) msb lsb (0e6h) msb lsb (0d6h) msb lsb (046h) msb lsb (036h) msb lsb (026h) msb lsb (016h) msb lsb (006h) msb lsb (0f5h) msb lsb (0e5h) msb lsb (0d5h) msb lsb (045h) msb lsb (035h) msb lsb (025h) msb lsb (015h) msb lsb (005h) msb lsb (0f4h) msb lsb (0e4h) msb lsb (0d4h) msb lsb (044h) msb lsb (034h) msb lsb (024h) msb lsb (014h) msb lsb (004h) msb lsb (0f3h) msb lsb (0e3h) msb lsb (0d3h) msb lsb (043h) msb lsb (033h) msb lsb (023h) msb lsb (013h) msb lsb (003h) msb lsb (0f2h) msb lsb (0e2h) msb lsb (0d2h) msb lsb (042h) msb lsb (032h) msb lsb (022h) msb lsb (012h) msb lsb (002h) msb lsb (0f1h) msb lsb (0e1h) msb lsb (0d1h) msb lsb (041h) msb lsb (031h) msb lsb (021h) msb lsb (011h) msb lsb (001h) msb lsb (0f0h) msb lsb (0e0h) msb lsb (0d0h) msb lsb (040h) msb lsb (030h) msb lsb (020h) msb lsb (010h) msb lsb (000h) msb s65 ------ s72 s57 ------ s64 s49 ------ s56 s41 ------ s48 s33 ------ s40 s25 ------ s32 s17 ------ s24 s9 -------- s16 s1 --------- s8 s73 ------ s80 c1 c2 c3 c12 c13 c14 c15 c16 ilc00200 msb (1f0h) lsb msb (1e0h) lsb msb (1d0h) lsb msb (140h) lsb msb (130h) lsb msb (120h) lsb msb (110h) lsb msb (100h) lsb msb (1f1h) lsb msb (1e1h) lsb msb (1d1h) lsb msb (141h) lsb msb (131h) lsb msb (121h) lsb msb (111h) lsb msb (101h) lsb msb (1f2h) lsb msb (1e2h) lsb msb (1d2h) lsb msb (142h) lsb msb (132h) lsb msb (122h) lsb msb (112h) lsb msb (102h) lsb msb (1f3h) lsb msb (1e3h) lsb msb (1d3h) lsb msb (143h) lsb msb (133h) lsb msb (123h) lsb msb (113h) lsb msb (103h) lsb msb (1f4h) lsb msb (1e4h) lsb msb (1d4h) lsb msb (144h) lsb msb (134h) lsb msb (124h) lsb msb (114h) lsb msb (104h) lsb msb (1f5h) lsb msb (1e5h) lsb msb (1d5h) lsb msb (145h) lsb msb (135h) lsb msb (125h) lsb msb (115h) lsb msb (105h) lsb msb (1f6h) lsb msb (1e6h) lsb msb (1d6h) lsb msb (146h) lsb msb (136h) lsb msb (126h) lsb msb (116h) lsb msb (106h) lsb msb (1f7h) lsb msb (1e7h) lsb msb (1d7h) lsb msb (147h) lsb msb (137h) lsb msb (127h) lsb msb (117h) lsb msb (107h) lsb bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 in this example, all ram is constructed like the following. msb lsb s1 ---------- s6 s7 --------- s12 s13 --------- s18 s19 --------- s24 s25 --------- s30 s31 --------- s36 s37 --------- s42 s43 --------- s48 c1 c2 c3 c12 c13 c14 c15 c16 ilc00201

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